1. Field of the Invention
The present invention relates to nonvolatile memory.
2. Description of the Prior Art
Recently, a nonvolatile memory device using ferroelectric devices is getting attention in the industry, and several structures of the device and circuit configuration for the device are proposed. FIG. 1 shows a structure of a nonvolatile memory cell which is disclosed in U.S. Pat. No. 4,888,733 where a transistor 18 and a transistor 20 are connected to either side of a ferroelectric capacitor 2. Gates of the transistor 18 and the transistor 20 are connected to a word line 8. Also, a source of the transistor 18 is connected to a bit line 14, and a source of the transistor 20 is connected with a bit line 16.
The ferroelectric capacitor 2 is polarized when a certain voltage is applied between the bit line 14 and the bit line 16 after turning on the transistor 18 and the transistor 20. Polarization of the ferroelectric capacitor 2 is maintained even after the voltage is no longer applied. The direction of polarization can be inverted by applying a voltage in the opposite direction. Accordingly, the ferroelectric capacitor 2 is able to store data under nonvolatile conditions.
When reading out the stored data from the capacitor, a certain voltage is applied to the ferroelectric capacitor 2. Upon applying the voltage to the ferroelectric capacitor 2, memorized polarization can be read by detecting whether the polarization inverts or not. In other words, memorized polarization can be read by detecting a current flowing when the polarization inverts. Since the memorized polarization is changed (i.e. stored data is erased) when reading out the data from the ferroelectric capacitor 2, the same data as the stored data is written back into the ferroelectric capacitor immediately after reading, in order to maintain the original polarization direction.
Furthermore, another nonvolatile memory device utilizing ferroelectric capacitors consisting of 2 ferroelectric capacitors and 2 transistors is proposed (disclosed in U.S. Pat. No. 4,873,664).
However, the nonvolatile memory devices discussed hereinabove have the following issues to resolve.
First, the memory device disclosed in U.S. Pat. No. 4,888,733 requires 2 transistors besides the ferroelectric capacitor for each cell. Therefore, the structure of the device is complicated. Moreover, the memory device disclosed in U.S. Pat. No. 4,873,664 requires 2 transistors and 2 ferroelectric capacitors for each cell, so that construction of the device is even more complicated.
Further, since the stored data in the ferroelectric capacitor is erased when reading out the data as described above, the same data (as the stored data) must be re-written into the capacitor, so control of the read operation is complex.